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????????????????????????????????????????????????????????????????? maxim integrated products 1 19-6254; rev 0; 3/12 ordering information appears at end of data sheet. for related parts and recommended products to use with this part, refer to www.maxim-ic.com/maxq615.related . maxq is a registered trademark of maxim integrated products, inc. note: some revisions of this device may incorporate deviations from published specifications known as errata. multiple revisions of any device may be simultaneously available through various sales channels. for information about device errata, go to: www.maxim-ic.com/errata . general description the maxq615 is a low-power, 16-bit maxq m microcon - troller designed for low-power applications. the device combines a powerful 16-bit risc microcontroller and integrated peripherals including multiple high-speed serial communication interfaces and flexible port i/o. high-speed communication interfaces include dual spi and i 2 c. the device also provides three instances of the 16-bit timer b peripheral. a 16 x 16 hardware multiply/ accumulate with 48-bit accumulator provides support for computationally intensive applications. the device provides 48kb of flash memory and 2kb of data sram. for the ultimate in low-power performance, the device includes an ultra-low-power stop mode (0.2 f a typ). in this mode, the minimum amount of circuitry is powered. wake-up sources include external interrupts, the power- fail interrupt, and a timer interrupt. the microcontroller runs from a single 2.4v to 3.6v power-supply operating voltage. applications portable computing battery-powered portable equipment consumer electronics home appliances white goods features s core functionality ? high-performance, low-power 16-bit maxq20s risc cor e ? dc to 20mhz operation across entire operating range ? 2.4v to 3.6v operating voltage ? three independent data pointers accelerate data movement with automatic inc/dec ? dedicated pointer for direct read from code space ? 16-bit instruction word, 16-bit data bus ? 16 x 16-bit general-purpose working registers ? optimized for c compiler s memory ? 48kb flash memory 1kb page sectors 20,000 erase/write cycles per sector ? 2kb data sram ? masked rom available s i/o and peripherals ? power-fail warning ? power-on reset/brownout reset ? three 16-bit programmable timers/counters with prescaler ? programmable watchdog timer ? internal 20mhz clock 5% ? dual spi ports with 16-byte fifo ? i 2 c communication port ? up to 12 general-purpose i/o pins s low power consumption ? 0.2a (typ) in stop mode ? 2.6ma (typ) at 20mhz ? divided system clock modes available maxq615 16-bit maxq microcontroller with hardware multiplier for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxims website at www.maxim-ic.com.
????????????????????????????????????????????????????????????????? maxim integrated products 2 maxq615 16-bit maxq microcontroller with hardware multiplier (all voltages relative to gnd.) voltage range on v dd ......................................... -0.3v to +3.6v voltage range on any lead .................... -0.3v to (v dd + 0.5v) continuous output current any single i/o pin...........................................................32ma all i/o pins combined..................................................... 32ma continuous power dissipation (t a = +70 n c) tqfn (derate 16.9mw/ n c above +70 n c) .................. 1349mw operating temperature range ......................... -40 n c to +85 n c storage temperature range .......................... -65 n c to +150 n c lead temperature (soldering, 10s) ........... +300 n c soldering temperature (reflow).... .. +260 n c absolute maximum ratings stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional opera - tion of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. recommended dc operating conditions (v dd = v rst to v dd(max) , t a = -40 n c to +85 n c, unless otherwise noted. typical values are measured at t a = +25 n c. ac electrical specifications and all specifications to t a = -40 n c are guaranteed by design and are not production tested.) parameter symbol conditions min typ max units supply voltage v dd v rst 3.6 v 1.8v internal regulator v reg18 1.62 1.7 1.98 v power-fail warning voltage v pfw monitors v dd (notes 1, 2) 2.45 2.6 2.75 v power-fail reset voltage v rst monitors v dd (note 3) 2.35 2.4 2.45 v power-on reset voltage v por monitors v dd 1.0 1.45 v supply current i dd1 f ck = 20mhz (note 4) 2.6 4.5 ma idle current i idle (note 5) 1.0 750 850 f a stop mode current i stop1 pf off t a = +25 n c 0.3 3.0 f a t a = 0 n c to +70 n c 1 12 t a = -40 n c to +85 n c 2 16 i stop2 pf on t a = +25 n c 22.0 35.0 t a = 0 n c to +70 n c 22.0 42.0 t a = -40 n c to +85 n c 22.0 45 stop mode resume time t on 300 f s power-fail monitor startup time t pfm_on (note 6) 150 f s power-fail warning detection time t pfw 10 f s clock source internal ring oscillator frequency f clk 5% 20 mhz ring oscillator duty cycle t clk_duty 45 55 % system clock frequency t ck f ck mhz system clock period f ck 1/f ck ns digital i/o input hysteresis v ihys v dd = 3.3v, t a = +25 n c 300 mv input low voltage v il v gnd 0.3 x v dd v input high voltage v ih 0.7 x v dd v dd v
????????????????????????????????????????????????????????????????? maxim integrated products 3 maxq615 16-bit maxq microcontroller with hardware multiplier spi electrical characteristics (v dd = 1.7v to 3.6v, t a = -40 n c to +85 n c, unless otherwise noted. ac electrical specifications are guaranteed by design and are not production tested.) ( figures 1 , 2 ) recommended dc operating conditions (continued) (v dd = v rst to v dd(max) , t a = -40 n c to +85 n c, unless otherwise noted. typical values are measured at t a = +25 n c. ac electrical specifications and all specifications to t a = -40 n c are guaranteed by design and are not production tested.) parameter symbol conditions min typ max units output low voltage (note 7) v ol v dd = 3.6v, i ol = 11ma 0.4 0.5 v v dd = 2.4v, i ol = 8ma 0.4 0.5 v output high voltage v oh i oh = -2ma (note 7) v dd - 0.5 v dd v input leakage current i l internal pullup disabled -100 +100 na input capacitance c io 15 pf input pullup resistance r pu v dd = 3.0v, v ol = 0.4v 16 28 39 k i flash memory system clock during flash programming 2 mhz flash erase time t me mass erase 20 40 ms t erase page erase 20 40 flash programming time per word t pmg 20 100 f s write/erase cycles 20,000 cycles data retention t a = +25 n c 100 years parameter symbol conditions min typ max units spi master operating frequency 1/t mck f ck /2 mhz spi slave operating frequency 1/t sck f ck /4 mhz spi i/o rise/fall time t spi_rf c l = 15pf, pullup = 560 w 8.3 23.6 ns sclk output pulse-width high/ low t mch , t mcl t mck /2 - t spi_rf ns mosi output hold time after sclk sample edge t moh t mck /2 - t spi_rf ns mosi output valid to sample edge t mov t mck /2 - t spi_rf ns miso input valid to sclk sample edge rise/fall setup t mis 25 ns miso input to sclk sample edge rise/fall hold t mih 0 ns sclk inactive to mosi inactive t mlh t mck /2 - t spi_rf ns
????????????????????????????????????????????????????????????????? maxim integrated products 4 maxq615 16-bit maxq microcontroller with hardware multiplier spi electrical characteristics (continued) (v dd = 1.7v to 3.6v, t a = -40 n c to +85 n c, unless otherwise noted. ac electrical specifications are guaranteed by design and are not production tested.) ( figures 1 , 2 ) figure 1. spi master communications timing parameter symbol conditions min typ max units sclk input pulse-width high/ low t sch , t scl t sck /2 ns ssel active to first shift edge t sse t spi_rf ns mosi input to sclk sample edge rise/fall setup t sis t spi_rf ns mosi input from sclk sample edge transition hold t sih t spi_rf ns miso output valid after sclk shift edge transition t sov 2t spi_rf ns ssel inactive t ssh t ck + t spi_rf ns sclk inactive to ssel rising t sd t spi_rf ns miso output disabled after ssel edge rise t slh 2t ck + 2t spi_rf ns ssel (sas = 0) mosi miso lsb lsb shift sample shift sample t mck t mch t moh t mis t mov t rf t mlh t mih t mcl msb msb-1 msb msb-1 sclk ckpol/ckpha sclk ckpol/ckpha 1/0 0/1 1/1 0/0 1/0 0/1 1/1 0/0
????????????????????????????????????????????????????????????????? maxim integrated products 5 maxq615 16-bit maxq microcontroller with hardware multiplier figure 2. spi slave communications timing i 2 c electrical characteristics (v dd = v rst to v dd(max) , t a = -40c to +85c, unless otherwise noted. ac electrical specifications and all specifications to t a = -40c are guaranteed by design and are not production tested.) ( figure 3 ) parameter symbol conditions standard mode fast mode units min max min max input low voltage v il_i2c supply voltages that mismatch i 2 c bus levels must relate input levels to the r p pullup voltage -0.5 0.3 x v dd -0.5 0.3 x v dd v input high voltage v ih_i2c supply voltages that mismatch i 2 c bus levels must relate input levels to the r p pullup voltage 0.7 x v dd 0.7 x v dd v dd + 0.5 v output logic-low (open drain or open collector) v ol_i2c v dd > 2v, 3ma sink current 0 0.4 0 0.4 v output fall time from v ih_min to v il_max with bus capacitance from 10pf to 400pf t of_i2c t r/f_i2c exceeds t of_i2c , which permits r s to be connected as shown in i 2 c bus controller timing table; c b = sda or scl capacitance in pf 250 20 + 0.1c b 250 ns shift sample shift sample ssel (sas = 1) mosi miso t sse t sck t sch t scl t sis t sov t slh t ssh t sd t rf t sih msb msb-1 msb msb-1 lsb lsb sclk ckpol/ckpha sclk ckpol/ckpha 1/0 0/1 1/1 0/0 1/0 0/1 1/1 0/0
????????????????????????????????????????????????????????????????? maxim integrated products 6 maxq615 16-bit maxq microcontroller with hardware multiplier i 2 c bus controller timing ( figure 4 ) i 2 c electrical characteristics (continued) (v dd = v rst to v dd(max) , t a = -40c to +85c, unless otherwise noted. ac electrical specifications and all specifications to t a = -40c are guaranteed by design and are not production tested.) ( figure 3 ) parameter symbol standard mode fast mode units min max min max i 2 c bus operating frequency f i2c 0 100 0 400 khz system frequency f sys 0.90 3.60 mhz i 2 c bit rate f i2c f sys /8 f sys /8 hz hold time after (repeated) start t hd:sta 4.0 0.6 f s clock low period t low_i2c 4.7 1.3 f s clock high period t high_i2c 4.0 0.6 f s setup time for repeated start t su:sta 4.7 0.6 f s hold time for data t hd:dat 0 3.45 0 0.9 f s setup time for data t su:dat 250 100 ns sda/scl fall time t f_i2c 300 20 + 0.1c b 300 ns sda/scl rise time t r_i2c 1000 20 + 0.1c b 300 ns setup time for stop t su:sto 4.0 0.6 f s bus free time between stop and start t buf 4.7 1.3 f s capacitive load for each bus line c b 400 400 pf noise margin at the low level for each connected device (including hysteresis) v nl_i2c 0.1 x v dd 0.1 x v dd v noise margin at the high level for each connected device (including hysteresis) v nh_i2c 0.2 x v dd 0.2 x v dd v parameter symbol conditions standard mode fast mode units min max min max pulse width of spike filtering that must be suppressed by input filter t sp_i2c 0 50 ns input current on i/o i in_i2c input voltage from 0.1 x v dd to 0.9 x v dd -10 +10 -10 +10 f a i/o capacitance c io_i2c 10 10 pf
????????????????????????????????????????????????????????????????? maxim integrated products 7 maxq615 16-bit maxq microcontroller with hardware multiplier figure 3. series resistors (r s ) for protecting against high-voltage spikes figure 4. i 2 c bus controller timing diagram note 1: the user application must check the status of the power-fail warning flag before writing to flash memory to ensure com - plete write operations. writes to flash memory must not be performed when the supply voltage drops below the power-fail warning levels. note 2: the power-fail warning monitor and the power-fail reset monitor track each other with a typical delta between the two of 0.13v at minimum power-fail warning selection. note 3: the power-fail reset and por detectors operate in tandem so one or both of these signals is active at all times when v dd < v rst , ensuring the device maintains the reset state until minimum operating voltage is achieved. note 4: measured on the v dd pin and the part not in reset. all inputs are connected to gnd or v dd . outputs do not source/sink any current. part is executing code from flash memory. note 5: measured on the v dd pin and the part not in reset. all inputs are connected to gnd or v dd . outputs do not source/sink any current. program execution is halted in idle mode. note 6: the minimum amount of time that v dd must be below v dd before a power-fail event is detected. refer to the user manual for detailed information. note 7: the maximum total current, i oh(max) and i ol(max) , for all listed outputs combined should not exceed 32ma to satisfy the maximum specified voltage drop. sda p0.7 scl p0.6 r s r s i 2 c device r s r s i 2 c device r p r p v dd maxq615 sda scl ss rp s t f_i2c t r_i2c t low_i2c t high_i2c t hd:sta t su:dat t su:sta t su:sto t buf t hd:dat note: timing referenced to v ih_i2c(min) and v il_i2c(max).
????????????????????????????????????????????????????????????????? maxim integrated products 8 maxq615 16-bit maxq microcontroller with hardware multiplier pin description pin configuration pin name function power pins 6 v dd digital supply voltage 8 gnd digital ground 7 reg18 regulator capacitor. this pin must be connected to ground through an external 1 f f external ceramic chip capacitor. this capacitor should be placed as close as possible to this pin. no other device may be attached to this pin. reset pins 1 reset active-low reset. this bidirectional pin recognizes external active-low reset inputs and employs an internal pullup resistor to allow for a combination of wired-or external reset sources. an rc is not required for power-up, as this function is provided internally. this pin also acts as an output when the source of the reset is internal to the device (e.g., watchdog timer, power-fail, etc). in this case, the pin is low while the processor is in a reset state, and returns high as the processor exits this state. 15 16 14 13 6 5 7 p0.0 / int0 / mosi0 p0.2/ int2/ sclk0 8 p0.6/ tms/ int6 p0.4/ tck/int4 p0.7/ tdo/ int7 12 p1.1/ miso1/ tbb0/int9 4 12 11 9 p1.2/ sclk1/ scl / tba1/int10 p1.3/ ssel1/ sda / tbb1/int11 gnd reg18 v dd p0.3/ int3/ ssel0 + p0.1/ int1/ miso0 p0.5/ tdi/int5 3 10 p1.0/ mosi1/ tba0/int8 maxq615 top view reset ep
????????????????????????????????????????????????????????????????? maxim integrated products 9 maxq615 16-bit maxq microcontroller with hardware multiplier pin description (continued) pin name function general-purpose i/o pins general-purpose, digital i/o pins. these port pins function as general-purpose i/o pins with their input and output states controlled by the pd0, po0, and pi0 registers. all port pins default to high-impedance mode after a reset. software must configure these pins after release from reset to remove the high-impedance condition. all alternate functions must be enabled from software before they can be used. alternate function description 2 p0.0 int0 external interrupt 0 mosi0 spi0: master out-slave in 3 p0.1 int1 external interrupt 1 miso0 spi0: master in-slave out 4 p0.2 int2 external interrupt 2 sclk0 spi0: spi clock 5 p0.3 int3 external interrupt 3 ssel0 spi0: slave select 9 p0.4 int4 external interrupt 4 tck jtag test clock 10 p0.5 int5 external interrupt 5 tdi jtag data in 11 p0.6 int6 external interrupt 6 tms jtag test mode select 12 p0.7 int7 external interrupt 7 tdo jtag data out 13 p1.0 int8 external interrupt 8 mosi1 spi1: master out-slave in tba0 timer b0 pin a 14 p1.1 int9 external interrupt 9 miso1 spi1: master in-slave out tbb0 timer b0 pin b 15 p1.2 int10 external interrupt 10 sclk1 spi1: spi clock scl i 2 c clock tba1 timer b1 pin a 16 p1.3 int11 external interrupt 11 ssel1 spi1: slave select sda i 2 c clock tbb1 timer b1 pin b exposed pad ep exposed pad. leave ep electrically unconnected.
???????????????????????????????????????????????????????????????? maxim integrated products 10 maxq615 16-bit maxq microcontroller with hardware multiplier block diagram detailed description the maxq615 is a maxq20s-based microcontroller that supports a variety of applications. one application would be power-supply sequencing and default voltage programming. it could also perform host interface control, backlight algorithm, fading control, and gas gauge algo - rithm functions. the microcontroller can add bootloader functionality to an application, making field updates much simpler. additionally, a low-power sleep mode makes this device ideal for battery-powered equipment. microprocessor the maxq20s core supports the harvard memory archi - tecture with separate 16-bit program and data address buses. a fixed 16-bit instruction word is standard, but data can be arranged in 8 or 16 bits. the maxq core is implemented as a pipelined processor with performance approaching 1mips per mhz. the 16-bit data path is implemented around register modules, and each register module contributes specific functions to the core. the accumulator module consists of sixteen 16-bit registers and is tightly coupled with the arithmetic logic unit (alu). program flow is supported by a configurable soft stack. execution of instructions is triggered by data transfer between functional register modules, or between a func - tional register module and memory. since data movement involves only source and destination modules, circuit switching activities are limited to active modules only. for power-conscious applications, this approach localizes power dissipation and minimizes switching noise. the modular architecture also provides a maximum of flexibil - ity and reusability that are important for a microprocessor used in embedded applications. the maxq instruction set is highly orthogonal. all arith - metic and logical operations can use any register in conjunction with the accumulator. data movement is sup - ported from any register to any other register. memory is accessed through specific data pointer registers with auto increment/decrement support. memory the microcontroller incorporates several memory types: ? 48kb flash memory ? 2kb sram ? 6kb utility rom ? ram-based software stack password-protected memory access some applications require preventative measures to protect against simple access and viewing of program code memory. to address this need for code protection, the device permits full access to in-system programming, in-application programming, or in-circuit debugging only after a password has been supplied. the password is defined as the 16 words of physical program memory at addresses 0010h - 001fh. these memory locations can be used for general code space if a unique password is not needed. when the password lock bit (pwl) is set to 1, password is required in order to access the rom loader utilities that support read/write accessing of internal memory and debug functions. when pwl is cleared to 0, these utili - ties are fully accessible through the utility rom without password. the pwl bit defaults to 1 by a power-on reset. in order to access the rom utilities, a correct password is needed; otherwise, access of rom utilities is denied. once the correct password has been supplied by the user, the rom clears the password lock. the pwl remains clear until a power-on reset occurs or it is set by application software. regulator 16-bit maxq risc cpu 20mhz ring oscillator voltage monitor 16-bit timer (3x) 16 x 16 mac spi (2x) watchdog jtag gpio i 2 c 6kb utility rom 48kb flash 2kb sram maxq615
???????????????????????????????????????????????????????????????? maxim integrated products 11 maxq615 16-bit maxq microcontroller with hardware multiplier the password can be entered through the bootloader interface selected by the pss1 and pss0 bits in sys - tem programming when the spe bit is set to logic 1, or selected through the tap interface directly by issuing a password-unlock command. utility rom the utility rom is a block of internal rom that defaults to a starting address of 8000h. the utility rom consists of subroutines that can be called from application software. these include the following: ? in-system programming using bootstrap loader ? read chip revision or manufacturer id ? test routines (internal memory tests, memory loader, etc.) ? user-callable routines for in-application flash pro - gramming and fast table lookup following any reset, execution begins in the utility rom. the rom software determines whether the program execution should immediately jump to location 0000h, the start of system code, or to one of the special routines mentioned. routines within the utility rom are user- accessible and can be called as subroutines by the application software. more information on the utility rom functions is contained in the user manual. loading flash memory with the bootstrap loader an internal bootstrap loader allows the device to be reloaded over the jtag interface. this allows software to be upgraded in-system, eliminating the need for a costly hardware retrofit when updates are required. remote software uploads are possible that enable physically inaccessible applications to be frequently updated. if in-system programmability is not required, a commercial gang programmer can be used for mass programming. watchdog timer an internal watchdog timer greatly increases system reli - ability. the timer resets the device if software execution is disturbed. the watchdog timer is a free-running coun - ter designed to be periodically reset by the application software. if software is operating correctly, the counter is periodically reset and never reaches its maximum count. however, if software operation is interrupted, the timer does not reset, triggering a system reset and option - ally a watchdog timer interrupt. this protects the system against electrical noise or electrostatic discharge (esd) upsets that could cause uncontrolled processor opera - tion. the internal watchdog timer is an upgrade to older designs with external watchdog devices, reducing sys - tem cost and simultaneously increasing reliability. the watchdog timer functions as the source of both the watchdog timer timeout and the watchdog timer reset. the timeout period can be programmed in a range of 215 to 232 system clock cycles. an interrupt is gener - ated when the timeout period expires if the interrupt is enabled. all watchdog timer resets follow the pro - grammed interrupt timeouts by 512 system clock cycles. if the watchdog timer is not restarted for another full interval in this time period, a system reset occurs when the reset timeout expires. table 1. watchdog timer intervals (f sysclk = 20mhz, cd[1:0] = 00) wd[1:0] watchdog interrupt timeout watchdog interrupt period (ms) watchdog reset after watchdog interrupt (s) 00 sysclk x 2 15 1.62 25.6 01 sysclk x 2 16 3.27 25.6 10 sysclk x 2 17 6.55 25.6 11 sysclk x 2 18 13.1 25.6
???????????????????????????????????????????????????????????????? maxim integrated products 12 maxq615 16-bit maxq microcontroller with hardware multiplier general-purpose i/o the general-purpose i/o pins have the following features: ? cmos output drivers ? schmitt trigger inputs ? optional weak pullup to v dd when operating in input mode while the microcontroller is in a reset state, all port pins become high impedance with input buffers and weak pullups disabled, unless otherwise noted. from a software perspective, each port appears as a group of peripheral registers with unique addresses. special function pins can also be used as general-pur - pose i/o pins when the special functions are disabled. for a detailed description of the special functions avail - able for each pin, refer to the user manual for this device. 16-bit timers/counters the microcontroller provides three timers/counters that support the following functions: ? 16-bit timer/counter ? 16-bit up/down autoreload ? counter function of external pulse ? 16-bit timer with capture ? 16-bit timer with compare ? input/output enhancements for pulse-width modulation ? set/reset/toggle output state on comparator match ? prescaler with 2n divider (for n = 0, 2, 4, 6, 8, 10) serial peripherals serial peripheral interface (spi) the device provides two spi ports. the spi is an inter - device bus protocol that provides fast, synchronous, full- duplex communications between devices. the integrated spi interface acts as either an spi master or slave device. the master drives the synchronous clock and selects which of several slaves is being addressed. every spi peripheral consists of a single shift register and control circuitry so that an addressed serial peripheral interface spi peripheral is simultaneously transmitting and receiv - ing. the maximum spi master transfer rate is sysclk/2. when operating as an spi slave, the device can support up to sysclk/4 spi transfer rate. data can be transferred as an 8-bit or 16-bit value, msb first. in addition, the spi module supports configuration of the active ssel state through the slave active-select pin. four signals are used in spi communication: ? sclk: the synchronous clock used by all devices. the master drives this clock and the slaves receive the clock. note that sclk can be gated and need not be driven between spi transactions. ? mosi: master out-slave in. this is the main data line driven by the master to all slaves on the spi bus. only the selected slave clocks data from mosi. ? miso: master in-slave out. this is the main data line driven by the selected slave to the master. only the selected slave may drive this circuit. in fact, it is the only circuit in the spi bus arrangement that a slave is ever permitted to drive. ? ssel: this signal is unique to each slave. when active (generally low), the selected slave must drive miso. i 2 c bus the microcontroller provides an internal i 2 c bus master/ slave for communication with a wide variety of other i 2 c-enabled peripherals. the i 2 c bus is a 2-wire, bidirec - tional bus using two bus linesthe serial data line (sda) and the serial clock line (scl)and a ground line. both the sda and sdl lines must be driven as open-collector/ drain outputs. external resistors are required to pull the lines to a logic-high state. the device supports both the master and slave proto - cols. in the master mode, the device has ownership of the i 2 c bus, drives the clock, and generates the start and stop signals. this allows it to send data to a slave or receive data from a slave as required. in slave mode, the device relies on an externally generated clock to drive scl and responds to data and commands only when requested by the i 2 c master device. hardware multiplier the internal hardware multiplier supports high-speed multiplications. the multiplier can complete a 16-bit x 16-bit multiply-and-accumulate/subtract operation in a single cycle with the support of a 48-bit accumulator. the multiplier is a fixed-point arithmetic unit. the operands can be either signed or unsigned numbers, but the data type must be defined by the application software prior to loading the operand registers.
???????????????????????????????????????????????????????????????? maxim integrated products 13 maxq615 16-bit maxq microcontroller with hardware multiplier seven different multiply operations can be performed with - out requiring direct intervention of the microcontroller core. ? unsigned 16-bit multiplication ? unsigned 16-bit multiplication and accumulation ? unsigned 16-bit multiplication and subtraction ? signed 16-bit multiplication ? signed 16-bit multiplication and negate ? signed 16-bit multiplication and accumulation ? signed 16-bit multiplication and subtraction each of these operations is controlled and accessed through six sfr registers. the 8-bit multiplier control reg - ister (mcnt) selects the operation, data type, operand count, optional hardware-based square function, write option on the mc register, the overflow flag, and the clear control for operand registers and accumulator. loading and unloading of the data is achieved through five 16-bit sfr registers. only one cycle is needed for computation. this means that the result of an operation is ready in the next cycle immediately following the loading of the last operand. back-to-back operations can be performed without wait states between operations, independent of data type and operand count. clock sources all operations are synchronized to a single internal sys - tem clock. the clock runs at approximately 20mhz. more information on the clock timing is contained in the electri - cal tables of this data sheet. internal clock divisors are available to reduce power consumption and or improve compatibility with slower peripherals. approximately 25s after v dd exceeds v rst (a power-on reset), the internal oscillator stabilzes and code execu - tion begins. in-circuit debug embedded debug hardware and software are developed and integrated to provide full in-circuit debugging capa - bility in a user application environment. these hardware and software features include: ? a debug engine ? a set of registers providing the ability to set break - points on register, code, or data using debug service routines stored in rom collectively, these hardware and software features sup - port two modes of in-circuit debug functionality: ? background mode: cpu is executing the normal user program allows the host to configure and set up the in-circuit debugger ? debug mode: the debugger takes over the control of the cpu read/write accesses to internal registers and mem - ory single-step of the cpu for trace operation the interface to the debug engine is the jtag interface. to prevent unauthorized access, the debug engine pre - vents access to system memory. operating modes idle mode the idle mode suspends the processor so that no instructions are fetched and no processing occurs. setting the idle bit in the ckcn register to 1 invokes the idle mode. the instruction that executes this step is the last instruction prior to halting the program counter. once in idle mode, all resources are preserved and all clocks remain active with the enabled peripherals, and power monitor continue to work, so the processor can exit the idle state using any of the interrupt sources that are enabled. the idle bit is cleared automatically once the idle state is exited, allowing the processor to execute the instruction that immediately follows the instruction that set the idle bit. to conserve power consumption, application can put the processor into idle mode when code execution is not required. one example of use is for spi communication. the application code can preload spi fifo with desired number of bytes for transmission and then put the pro - cessor into idle mode. the device continues with the spi transaction and only interrupts the processor when the enabled spi interrupts are generated. another use is to configure one of the timers to interrupt the device at a predetermined interval. the application code can finish its task and then put the processor into idle mode. the timer then wakes up the processor when the specified interval has elapsed.
???????????????????????????????????????????????????????????????? maxim integrated products 14 maxq615 16-bit maxq microcontroller with hardware multiplier stop mode the lowest power mode of operation for the device is stop mode. in this mode, cpu state and memories are preserved, but the cpu is not actively running. wake-up sources include external i/o interrupts, the power-fail warning interrupt, or a power-fail reset. any time the microcontroller is in a state where code does not need to be executed, the user software can put the device into stop mode. the nanopower ring oscillator is an internal ultra-low-power (400na), 8khz ring oscillator that can be used to drive a wake-up timer that exits stop mode. the wake-up timer is programmable by software in steps of 125s up to approximately 8s. the power-fail monitor is always on during normal oper- ation. however, it can be selectively disabled during stop mode to minimize power consumption. this feature is enabled using the power-fail monitor disable (pfd) bit in the pwcn register. the reset default state for the pfd bit is 1, which disables the power-fail monitor function during stop mode. if power-fail monitoring is dis - abled (pfd = 1) during stop mode, the circuitry respon - sible for generating a power-fail warning or reset is shut down and neither condition is detected. thus, the v dd < v rst condition does not invoke a reset state. however, in the event that v dd falls below the por level, a por is generated. the power-fail monitor is enabled prior to stop mode exit and before code execution begins. if a power-fail warning condition (v dd < v pfw ) is then detected, the power-fail interrupt flag is set on stop mode exit. if a power-fail condition is detected (v dd < v rst ), the cpu goes into reset. power-fail detection figure 5 , 6 , and 7 show the power-fail detection and response during normal and stop mode operation. figure 5. power-fail detection during normal operation a b c d f g h i e v dd v pfw v rst v por internal reset (active high) t < t pfw t r t pfw t r t pfw t r t pfw
???????????????????????????????????????????????????????????????? maxim integrated products 15 maxq615 16-bit maxq microcontroller with hardware multiplier if a reset is caused by a power-fail, the power-fail moni- tor can be set to one of the following intervals: ? always oncontinuous monitoring ? 2 11 nanopower ring oscillator clocks (~256ms) ? 2 12 nanopower ring oscillator clocks (~512ms) ? 2 13 nanopower ring oscillator clocks (~1.024s) in the case where the power-fail circuitry is periodically turned on, the power-fail detection is turned on for two nanopower ring oscillator cycles. if v dd > v rst during detection, v dd is monitored for an additional nanopow- er ring oscillator period. if v dd remains above v rst for the third nanopower ring period, the cpu exits the reset state and resumes normal operation from utility rom at 8000h after satisfying the crystal warmup period. if a reset is generated by any other event, such as the reset pin being driven low externally or the watchdog timer, the power-fail, internal regulator, and crystal remain on during the cpu reset. in these cases, the cpu exits the reset state in less than 20 crystal cycles after the reset source is removed. table 2. power-fail detection states during normal operation state power-fail internal regulator crystal oscillator sram retention comments a on off off v dd < v por . b on on on v por < v dd < v rst . crystal warmup time, t xtal_rdy . cpu held in reset. c on on on v dd > v rst . cpu normal operation. d on on on power drop too short. power-fail not detected. e on on on v rst < v dd < v pfw . pfi is set when v rst < v dd < v pfw and maintains this state for at least t pfw , at which time a power- fail interrupt is generated (if enabled). cpu continues normal operation. f on (periodically) off off yes v por < v dd < v rst . power-fail detected. cpu goes into reset. power-fail monitor turns on periodically. g on on on v dd > v rst . crystal warmup time, t xtal_rdy . cpu resumes normal operation from 8000h. h on (periodically) off off yes v por < v dd < v rst . power-fail detected. cpu goes into reset. power-fail monitor is turned on periodically. i off off off v dd < v por . device held in reset. no operation allowed.
???????????????????????????????????????????????????????????????? maxim integrated products 16 maxq615 16-bit maxq microcontroller with hardware multiplier figure 6. stop mode power-fail detection states with power-fail monitor enabled table 3. stop mode power-fail detection states with power-fail monitor enabled state power-fail internal regulator crystal oscillator sram retention comments a on off off yes application enters stop mode. v dd > v rst . cpu in stop mode. b on off off yes power drop too short. power-fail not detected. c on on on yes v rst < v dd < v pfw . power-fail warning detected. turn on regulator and crystal. crystal warmup time, t xtal_rdy . exit stop mode. d on off off yes application enters stop mode. v dd > v rst . cpu in stop mode. e on (periodically) off off yes v por < v dd < v rst . power-fail detected. cpu goes into reset. power-fail monitor is turned on periodically. f off off off v dd < v por . device held in reset. no operation allowed. v pfw v rst v por a b c d e f v dd t < t pfw t r t pfw t r t pfw stop internal reset (active high)
???????????????????????????????????????????????????????????????? maxim integrated products 17 maxq615 16-bit maxq microcontroller with hardware multiplier figure 7. stop mode power-fail detection with power-fail monitor disabled table 4. stop mode power-fail detection states with power-fail monitor disabled state power-fail internal regulator crystal oscillator sram retention comments a off off off yes application enters stop mode. v dd > v rst . cpu in stop mode. b off off off yes v dd < v pfw . power-fail not detected because power-fail monitor is disabled. c on on on yes v rst < v dd < v pfw . an interrupt occurs that causes the cpu to exit stop mode. power-fail monitor is turned on, detects a power-fail warning, and sets the power-fail interrupt flag. turn on regulator and crystal. crystal warmup time, t xtal_rdy . on stop mode exit, cpu vectors to the higher priority of power-fail and the interrupt that causes stop mode exit. v pfw v rst v por v dd a b c d e f stop internal reset (active high) interrupt
???????????????????????????????????????????????????????????????? maxim integrated products 18 maxq615 16-bit maxq microcontroller with hardware multiplier table 4. stop mode power-fail detection states with power-fail monitor disabled (continued) applications information the low-power, high-performance risc architecture of this device makes it an excellent fit for many portable or applications requiring security. grounds and bypassing careful pcb layout significantly minimizes system level digital noise that could interact with the microcontroller or peripheral components. the use of multilayer boards is essential to allow the use of dedicated power planes. the area under any digital components should be a continu - ous ground plane if possible. keep any bypass capacitor leads short for best noise rejection and place the capaci - tors as close to the leads of the devices as possible. cmos design guidelines for any semiconductor require that no pin be taken above v dd or below gnd. violation of this guideline can result in a hard failure (damage to the silicon inside the device) or a soft failure (uninten - tional modification of memory contents). voltage spikes above or below the devices absolute maximum ratings can potentially cause a catastrophic latchup of the device. microcontrollers commonly experience negative volt - age spikes through either their power pins or general- purpose i/o pins. negative voltage spikes on power pins are especially problematic as they directly couple to the internal power buses. devices such as keypads can con - duct electrostatic discharges directly into the microcon - troller and seriously damage the device. system design - ers must protect components against these transients that can corrupt system memory. additional documentation designers must have the following documents to fully use all the features of this device. this data sheet contains pin descriptions, feature overviews, and electrical specifications. errata sheets contain deviations from published specifications. the users guide offers detailed information about device features and operation. ? this maxq615 data sheet, which contains electrical/ timing specifications and pin descriptions. ? the revision-specific maxq615 errata sheet. ? the maxq615 users guide, which contains detailed information on core features and operation, including programming. development and technical support a variety of highly versatile, affordably-priced develop - ment tools for this microcontroller are available from maxim and third-party suppliers, including: ? compilers ? in-circuit emulators ? integrated development environments (ides) a partial list of development tool vendors can be found at www.maxim-ic.com/maxq?tools . for technical support, go to: https://support.maxim-ic.com/micro . state power-fail internal regulator crystal oscillator sram retention comments d off off off yes application enters stop mode. v dd > v rst . cpu in stop mode. e on (periodically) off off yes v por < v dd < v rst . an interrupt occurs that causes the cpu to exit stop mode. power-fail monitor is turned on, detects a power- fail, puts cpu in reset. power-fail monitor is turned on periodically. f off off off v dd < v por device held in reset. no operation allowed.
???????????????????????????????????????????????????????????????? maxim integrated products 19 maxq615 16-bit maxq microcontroller with hardware multiplier package information for the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. chip information process: bicmos ordering information + denotes a lead(pb)-free/rohs-compliant package. * ep = exposed pad. part operating voltage (v) temp range flash memory (kb) data memory (kb) pin-package MAXQ615-F00+ 2.4 to 3.6 -40 n c to +85 n c 48 2 16 tqfn-ep* package type package code outline no. land pattern no. 16 tqfn-ep t1644+4 21-0139 90-0070
maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. the parametric values (min and max limits) shown in the electrical characteristics table are guaranteed. other parametric values quoted in this data sheet are provided for guidance. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 20 ? 2012 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. revision history revision number revision date description pages changed 0 3/12 initial release maxq615 16-bit maxq microcontroller with hardware multiplier

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